1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a notch located at an end of an isolating and insulating film neighboring to an impurity region as well as a method of manufacturing the same.
2. Description of the Background Art
In recent years, demands for semiconductor memory devices have been rapidly increased owing to remarkable spread of information equipments such as computers. In connection with function, devices having a large scale storage capacity and allowing fast operation have been demanded. In compliance with these demands, technologies have been developed for improving degree of integration, response and reliability of the semiconductor memory devices.
Dynamic random access memories (DRAMs) have been known as a kind of semiconductor memory devices which enable random input and output of storage information. In general, the DRAM is formed of a memory cell array, which is a storage region storing a large number of storage information, and a peripheral circuitry required for external input and output.
The memory cell array is provided with a plurality of memory cells each storing unit storage information and arranged in a matrix form. The memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto, and hence is of a so-called one-transistor and one-capacitor type. Since this type of memory cell has a simple structure, the degree of integration of memory cell array can be increased easily, and hence is widely used in a DRAM of a large capacity. FIG. 81 is a cross section of this memory cell, and FIG. 82 is a plan of the same. FIG. 81 shows a section taken along line 81--81 in FIG. 82, and FIG. 82 shows a view taken along line 82--82 in FIG. 81.
The structure shown in FIGS. 81 and 82 is of a buried bit line stacked type memory cell in which a bit line is buried.
Referring to FIGS. 81 and 82, the structure of memory cell will be described below. A p type semiconductor substrate 1 made of, e.g., silicon is provided at its main surface with an element isolating oxide film 2 made of, e.g., SiO.sub.2 for defining an active region. At the active region, there are formed the memory cells each including one transfer gate transistor 100 and one stacked type capacitor 200 paired to each other.
Transfer gate transistor 100 includes first and second impurity regions 5 and 6 formed at the main surface of semiconductor substrate 1 and forming source/drain regions, and also includes a gate oxide film 3 formed on the main surface of semiconductor substrate 1 and made of, e.g., SiO.sub.2, and a gate electrode (word line) 4 made of, e.g., polycrystalline silicon and formed on the main surface with gate oxide film 3 therebetween. First impurity region 5 has a two-layer structure including a high concentration impurity region 5a and a low concentration impurity region 5b. Second impurity region 6 is formed of a high concentration impurity region. Gate electrode 4 is covered with a side wall insulating film 8 made of, e.g., SiO.sub.2.
Semiconductor substrate 1 is covered with a first interlayer oxide film 9 made of, e.g., SiO.sub.2 and having a film thickness of about 8000 .ANG.. A storage node contact hole 10 exposing second impurity region 6 and a bit line contact hole 11 exposing first impurity region 5 are formed at first interlayer oxide film 9. In bit line contact hole 11, there is formed a bit line 7 connected to first impurity region 5. Bit line 7 is formed of a doped polycrystalline silicon film 7a of about 1000 .ANG. in thickness and a tungsten silicide film 7b of about 1000 .ANG. in thickness.
On first interlayer oxide film 9, there is formed a second interlayer oxide film 13 of about 10000 .ANG. in thickness having storage node contact hole 10 and made of, e.g., SiO.sub.2. In storage node contact hole 10, there is formed a storage node (lower electrode) 12 made of, e.g., polycrystalline silicon and having a portion of about 6000 .ANG. in thickness located on second interlayer oxide film 13. Over the surface of storage node 12, there is formed a dielectric film 14, on which a cell plate (upper electrode) 15 is formed. Storage node 12, dielectric film 14 and cell plate 15 form stacked type capacitor 200. Above cell plate 15, there are formed interconnection layers 17 with a third interlayer oxide film 16 therebetween.
Then, a method of manufacturing the memory cell thus constructed will be described below with reference to FIGS. 84 to 95.
Referring first to FIG. 83, element isolating oxide film 2 is formed at predetermined regions on the main surface of semiconductor substrate 1 by the LOCOS method. Then, as shown in FIG. 84, gate electrodes 4 of a predetermined configuration are formed at predetermined regions on semiconductor substrate 1 with gate oxide films 3 made of, e.g., SiO.sub.2 therebetween.
Referring to FIG. 85, a resist film 20, which exposes a predetermined region between parallel gate electrodes 4, is formed on semiconductor substrate 1. Using resist film 20 as a mask, n type impurity such as phosphorus is implanted into semiconductor substrate 1 with an implantation dose of about 2.3.times.10.sup.13 cm.sup.2 and an implantation energy of about 35 keV to form low concentration impurity region 5b.
Referring to FIG. 86, SiO.sub.2 is deposited on semiconductor substrate 1 and anisotropic etching is effected thereon, so that side wall 8 is formed over gate electrode 4. Using side wall 8 as a mask, n type impurity such as phosphorus is implanted into the main surface of semiconductor substrate 1 with an implantation dose of about 4.times.10.sup.13 cm.sup.2 and an implantation energy of about 40 keV to form high concentration impurity regions 5a and 6 as shown in FIG. 87. Thereby, first impurity region 5 formed of high concentration impurity region 5a and low concentration impurity region 5b as well as second impurity region 6 formed of the high concentration impurity region are completed.
Referring to FIG. 88, first interlayer oxide film 9 made of, e.g., SiO.sub.2 and having a thickness of about 8000 .ANG. is deposited over semiconductor substrate 1 by the CVD method.
Referring to FIG. 89, a resist film 22 having an opening located above first impurity region 5 is formed on first interlayer oxide film 9. Using resist film 22 as a mask, bit line contact hole 11 is formed by the self-align contact method.
Referring to FIG. 90, after removing resist film 22, doped polycrystalline silicon film 7a and tungsten silicide film 7b each having a thickness of about 1000 .ANG. are deposited in bit line contact hole 11 and are patterned into a predetermined configuration to form bit line 7.
Referring to FIG. 91, second interlayer oxide film 13 of about 10000 .ANG. in thickness made of, e.g., SiO.sub.2 is formed on first interlayer oxide film 9. Then, a resist film 23 having openings each located above second impurity region 6 is formed on second interlayer oxide film 13. Using resist film 23 as a mask, storage node contact hole 10 is formed at first and second interlayer oxide films 9 and 13 by the self-align contact method.
Referring to FIG. 92, after removing resist film 23, polycrystalline silicon or the like is deposited in storage node contact hole 10 to form storage node 12 having the portion of about 6000 .ANG. in thickness located on second interlayer oxide film 13.
Referring to FIG. 93, dielectric film 14 and cell plate 15 are deposited over storage node 12. Thereby, stacked type capacitor 200 formed of storage node 12, dielectric film 14 and cell plate 15 is completed. Referring to FIG. 94, third interlayer oxide film 16 made of, e.g., SiO.sub.2 is then formed on cell plate 15, and interconnection layers 17 having a predetermined configuration are formed on third interlayer oxide film 16, whereby the memory cell shown in FIG. 81 is completed.
The DRAM described above stores data by storing electric charges in the capacitor. When data of, e.g., "H" is stored, a problem may arise in connection with leak of a current from the storage node, so that refresh operation must be performed periodically in the DRAM. Although it is preferable that a cycle of the refresh operation of the DRAM is long, there is nowadays a tendency that the cycle becomes short due to a tendency that the capacity of capacitor in the memory cell decreases in accordance with increase of the degree of integration of the DRAM. Therefore, it is necessary to prevent the leak of current from the storage node in order to maintain the long cycle of refresh operation even if the degree of integration of the DRAM is high.
Referring to FIG. 95, description will be given on a leak path of the current from the storage node in the structure of the memory cell described above.
The current may leak from storage node 12 via the following paths:
(1) Through second impurity region 6 to semiconductor substrate 1. PA1 (2) Through second impurity region 6 under gate electrode 4 to first impurity region 5. PA1 (3) To cell plate 15.
Among these paths, the path (1) through second impurity region 6 to semiconductor substrate 1 is the predominant path. The leak to semiconductor substrate 1 is the same as that caused when a reverse bias is applied to a pn junction. However, in the steps of forming isolating oxide film 2 and implanting impurity into first and second impurity regions 5 and 6, so-called crystal defects are generated at semiconductor substrate 1. If the crystal defects are generated at the pn junction, a new leak path is formed at this region. As a result, the electric charges stored in the capacitor are discharged through this new leak path, resulting in failure in data holding by the DRAM.
In particular, many crystal defects 2b are generated at an edge portion of isolating oxide film 2, i.e., a so-called bird's beak 2a. Crystal defects 2b can be removed by a heat treatment aimed at removal of the crystal defects after the step of implanting impurity. However, the process must be performed at a lower temperature as the degree of integration of DRAM increases, so that it is difficult to remove completely the crystal defects.